HD64F2166VTE33 Renesas Electronics America, HD64F2166VTE33 Datasheet - Page 482
HD64F2166VTE33
Manufacturer Part Number
HD64F2166VTE33
Description
IC H8S MCU FLASH 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2166VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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If IIC is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is
transferred automatically from ICDRS to ICDRR, following reception of one frame of data using
ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically
from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from
ICDRS to ICDRR. Always set IIC to receive mode before reading from ICDR.
If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data
and receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should
be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1.
ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value
of ICDR is undefined.
15.3.2
SAR sets the slave address and selects the communication format. When the LSI is in slave mode
with the I
upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device
specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to
0.
Rev. 3.00, 03/04, page 440 of 830
Bit
7
6
5
4
3
2
1
0
Bit Name
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
2
Slave Address Register (SAR)
C bus format selected, if the FS bit is set to 0 and the upper 7 bits of SAR match the
Initial
Value
All 0
0
R/W
R/W
R/W
Description
Slave Address
Set a slave address.
Format Select
Selects the communication format together with the FSX
bit in SARX. Refer to table 15.2.
This bit should be set to 0 when general call address
recognition is performed.
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