HD64F2166VTE33 Renesas Electronics America, HD64F2166VTE33 Datasheet - Page 68
HD64F2166VTE33
Manufacturer Part Number
HD64F2166VTE33
Description
IC H8S MCU FLASH 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2166VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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2.4.4
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Rev. 3.00, 03/04, page 26 of 830
Bit
7
6
5
4
3
2
1
Bit Name
I
UI
H
U
N
Z
V
Condition-Code Register (CCR)
Initial Value
1
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W Description
R/W Interrupt Mask Bit
R/W User Bit or Interrupt Mask Bit
R/W Half-Carry Flag
R/W User Bit
R/W Negative Flag
R/W Zero Flag
R/W Overflow Flag
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to 1
at the start of an exception-handling sequence. For details,
see section 5, Interrupt Controller.
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed, this flag is set to 1 if there is
a carry or borrow at bit 3, and cleared to 0 otherwise. When
the ADD.W, SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry or borrow
at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag
is set to 1 if there is a carry or borrow at bit 27, and cleared
to 0 otherwise.
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
Stores the value of the most significant bit of data as a sign
bit.
Set to 1 to indicate zero data, and cleared to 0 to indicate
non-zero data.
Set to 1 when an arithmetic overflow occurs, and cleared to
0 otherwise.
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