DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1050

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 26 User Debugging Interface (H-UDI)
26.3.2
SDIR is a 16-bit read-only register. It is initialized by UDTRST assertion, in the TAP test-logic-
reset state or in deep standby mode, and can be written to by the H-UDI irrespective of the CPU
mode. Operation is not guaranteed if a reserved command is set in this register. The initial value is
H'EFFD.
Note:
Table 26.3 H-UDI Commands
Page 1022 of 1190
Bit
15 to 8
7 to 2
1
0
TI7
0
0
1
1
1
Other than above
Initial value:
Note: *
R/W:
Bit:
* The initial value of the TI[7:0] bits is a reserved value. When setting a command, the
TI6
1
1
0
0
1
Instruction Register (SDIR)
The initial value of the TI[7:0] bits is a reserved value. When setting a command, the TI[7:0] bits must be set to
another value.
TI[7:0] bits must be set to another value.
Bit Name
TI[7:0]
⎯
⎯
⎯
15
1*
R
14
TI5
1
1
0
1
1
1*
R
13
1*
R
Initial Value
11101111*
All 1
0
1
0
1
1
1
TI4
1
Bits 15 to 8
12
0*
R
TI[7:0]
11
1*
R
—
—
1
—
—
TI3
R/W
R
R
R
R
10
1*
R
TI2
—
—
1
—
—
1*
R
9
Description
Test Instruction
The H-UDI instruction is transferred to SDIR by a
serial input from UDTDI.
For commands, see table 26.3.
Reserved
These bits are always read as 1.
Reserved
This bit is always read as 0.
Reserved
This bit is always read as 1.
1*
R
8
TI1
—
—
0
—
—
R
7
1
TI0
—
—
0
—
—
R
6
1
R
5
1
Description
H-UDI reset negate
H-UDI reset assert
UDTDO change timing switch
H-UDI interrupt
BYPASS mode
Reserved
R
4
1
R01UH0026EJ0300 Rev. 3.00
R
3
1
R
2
1
SH7201 Group
Sep 24, 2010
R
1
0
R
0
1