DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1058

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 27 Advanced User Debugger II (AUD-II)
27.3.2
Operation starts in RAM monitor mode when AUDRST is asserted, AUDMD is driven high, and
then AUDRST is negated.
Figure 27.2 shows an example of a read operation, and figure 27.3 shows an example of a write
operation.
When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address,
or data (writing only) is input in the format shown in figure 27.1, execution of read/write access to
the specified address is started. During internal execution, the AUD returns Not Ready (B'0000).
When execution is completed, the Ready flag (B'0001) is returned (figures 27. 2 and 27. 3). Table
27.3 shows the Ready flag format.
In a read, data of the specified size is output when AUDSYNC is negated following detection of
this flag (figure 27. 2).
If a command other than the above is input in DIR, the AUD-II treats this as a command error,
disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the
command specified in DIR causes a bus error, the AUD-II disables processing and sets bit 2 in the
Ready flag to 1 (figure 27. 4).
Bus error conditions are shown below.
1. Word access to address 4n+1 or 4n+3
2. Longword access to address 4n+1, 4n+2, or 4n+3
Table 27.3 Ready Flag Format
Page 1030 of 1190
Bit 3
Fixed at 0
Operation
Bit 2
0: Normal status
1: Bus error
Bit 1
0: Normal status
1: Command error
Bit 0
0: Not ready
1: Ready
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010