DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 11

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
Section 6 Interrupt Controller (INTC) ...............................................................115
6.1
6.2
6.3
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
5.2.2
5.2.3
5.2.4
Address Errors .................................................................................................................. 101
5.3.1
5.3.2
Bus Error........................................................................................................................... 103
5.4.1
5.4.2
Register Bank Errors......................................................................................................... 104
5.5.1
5.5.2
Interrupts........................................................................................................................... 105
5.6.1
5.6.2
5.6.3
Exceptions Triggered by Instructions ............................................................................... 108
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
When Exception Sources Are Not Accepted .................................................................... 111
Stack Status after Exception Handling Ends..................................................................... 112
Usage Notes ...................................................................................................................... 114
5.10.1
5.10.2
5.10.3
Features............................................................................................................................. 115
Input/Output Pins.............................................................................................................. 117
Register Descriptions ........................................................................................................ 117
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Types of Reset .................................................................................................... 97
Power-On Reset .................................................................................................. 98
Manual Reset .................................................................................................... 100
Address Error Sources ...................................................................................... 101
Address Error Exception Handling ................................................................... 102
Bus Error Generation Source ............................................................................ 103
Bus Error Exception Handling.......................................................................... 103
Register Bank Error Sources............................................................................. 104
Register Bank Error Exception Handling ......................................................... 104
Interrupt Sources............................................................................................... 105
Interrupt Priority Level ..................................................................................... 106
Interrupt Exception Handling............................................................................ 107
Types of Exceptions Triggered by Instructions ................................................ 108
Trap Instructions ............................................................................................... 109
Slot Illegal Instructions ..................................................................................... 109
General Illegal Instructions............................................................................... 109
Integer Division Exceptions.............................................................................. 110
FPU Exceptions ................................................................................................ 110
Value of Stack Pointer (SP) .............................................................................. 114
Value of Vector Base Register (VBR) .............................................................. 114
Address Errors Caused by Stacking of Address Error Exception Handling ..... 114
Interrupt Priority Registers 01, 02, 05 to 16
(IPR01, IPR02, IPR05 to IPR16) ...................................................................... 119
Interrupt Control Register 0 (ICR0).................................................................. 121
Interrupt Control Register 1 (ICR1).................................................................. 122
Interrupt Control Register 2 (ICR2).................................................................. 123
IRQ Interrupt Request Register (IRQRR)......................................................... 123
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