DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1192
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Main Revisions for This Edition
Page 1164 of 1190
Item
5.7.1 Types of Exceptions
Triggered by Instructions
Table 5.10 Types of Exceptions
Triggered by Instructions
5.7.5 Integer Division Exceptions 110
5.7.6 FPU Exceptions
Page
108
110
Revision (See Manual for Details)
Table amended
Title and description amended
1. The exception service routine start address which
Title and description amended
An FPU exception handling is generated when the V,
Z, O, U or I bit in the FPU exception enable field
(Enable) of the floating point status/control register
(FPSCR) is set. This indicates the occurrence of an
invalid operation exception defined by the IEEE
standard 754, a division-by-zero exception, overflow
(in the case of an instruction for which this is
possible), underflow (in the case of an instruction for
which this is possible), or inexact exception (in the
case of an instruction for which this is possible).
The floating-point operation instructions that may
cause generation of an FPU exception handling are
FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ,
FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, and
FSQRT.
An FPU exception handling is generated only when
the corresponding FPU exception enable bit (Enable)
is set. When the FPU detects an exception source by
a floating-point operation, FPU operation is halted and
FPU exception handling generation is reported to the
CPU. When exception handling is started, the CPU
operations are as follows.
1. The
Type
FPU exceptions
corresponds to the integer division
that occurred is fetched from the exception
handling vector table.
routine which corresponding to the FPU exception
handling that occurred is fetched from the
exception handling vector table.
start address of the exception service
Source Instruction
Instructions that cause disabled
operation exception defined by
IEEE754 standard or division
exception by zero. Instructions
that could cause overflow,
underflow, or imprecise
exception.
Comment
FADD, FSUB, FMUL, FDIV, FMAC,
FCMP/EQ, FCMP/GT, FLOAT, FTRC,
FCNVDS, FCNVSD, FSQRT
R01UH0026EJ0300 Rev. 3.00
exception
SH7201 Group
Sep 24, 2010
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