DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1204

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Main Revisions for This Edition
Page 1176 of 1190
Item
19.2.1 Block Diagram
19.4.3 Bit Configuration Register
(BCR0, BCR1)
•
19.4.4 Interrupt Request Register
(IRR)
19.6.1 Configuration of RCAN-
ET
Figure 19.6 Reset Sequence
20.3.2 A/D Control/Status
Register (ADCSR)
BCR0 (Address = H'006)
Page
814
834
836
839
859
885
Revision (See Manual for Details)
Description amended
Important: Although core of RCAN-ET is designed
based on a 32-bit bus system, the whole RCAN-ET
including MPI for the CPU has 16-bit bus interface to
CPU.
into two consecutive word accesses by the bus
interface.
Description amended
Where: BRP (Baud Rate Pre-scaler) is the value
stored in BCR0 incremented by 1 and fclk is the used
peripheral clock frequency.
Description amended
Bits 7 to 0—Baud Rate Pre-scale (BRP[7:0] = BCR0
[7:0]): These bits are used to define the peripheral
clock periods contained in a Time Quantum.
Table amended
Description amended
The interrupt request register (IRR) is a 16-bit
read/write-clearable register containing status flags for
the various interrupt sources.
Figure amended
Notes: 3. It takes approximately one bit time for
Table amended
Bit
2 to 0
Bit 7:
BRP[7]
0
0
0
:
:
1
Bit 6:
BRP[6]
0
0
0
:
:
1
Bit Name
CH[2:0]
GSR[3] to be cleared to 0.
Bit 5:
BRP[5]
0
0
0
:
:
1
LongWord (32-bit) accesses are converted
Initial
Value
000
Bit 4:
BRP[4]
0
0
0
:
:
1
R/W
R/W
Bit 3:
BRP[3]
0
0
0
:
:
1
Description
Channel Select
These bits and the MDS bits in ADCSR select the
analog input channels.
MDS = 0xx
000: AN0
001: AN1
010: AN2
011: AN3
100: AN4
101: AN5
110: AN6
111: AN7
Bit 2:
BRP[2]
0
0
0
:
:
1
Bit 1:
BRP[1]
0
0
1
:
:
1
R01UH0026EJ0300 Rev. 3.00
MDS = 100 or
MDS = 110
000: AN0
001: AN0, AN1
010: AN0 to AN2
011: AN0 to AN3
100: AN4
101: AN4, AN5
110: AN4 to AN6
111: AN4 to AN7
Bit 0:
BRP[0]
0
1
0
:
:
1
Description
2
(Initial value)
4
6
2
peripheral clock
512
(register value+1)
peripheral
peripheral
peripheral
SH7201 Group
peripheral
MDS = 101 or
MDS = 111
000: AN0
001: AN0, AN1
010: AN0 to AN2
011: AN0 to AN3
100: AN0 to AN4
101: AN0 to AN5
110: AN0 to AN6
111: AN0 to AN7
Sep 24, 2010
clock
clock
clock
clock