DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1209

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
29.3.3 Bus Timing
Figure 29.16 Single Write Bus
Timing for SDRAM Space (DCL =
2 (Two Cycles), DRCD = 1 (Two
Cycles), DPCG = 1 (Two Cycles))
Figure 29.17 Multiple Read Bus
Timing for SDRAM Space (Four
Data Access, DCL = 2 (Two
Cycles), DRCD = 1 (Two Cycles),
DPCG = 1 (Two Cycles))
Figure 29.18 Multiple Write Bus
Timing for SDRAM Space (Four
Data Access, DCL = 2 (Two
Cycles), DRCD = 1 (Two Cycles),
DPCG = 1 (Two Cycles))
Figure 29.19 Multiple Read Row
Span Bus Timing for SDRAM
Space (Eight Data Access, DCL =
2 (Two Cycles), DRCD = 1 (Two
Cycles), DPCG = 1 (Two Cycles))
29.3.6 MTU2 Module Timing
Table 29.10 MTU2 Module
Timing
29.6 Usage Note
Figure 29.49 Example of
Externally Allocated Capacitors
Item
Page
1130
1131
1132
1133
1138
1153
Revision (See Manual for Details)
Figure title amended
Figure title amended
Figure title amended
Figure title amended
Table amended
Note amended
Note:
Figure amended
Item
Output compare output delay time
Input capture input setup time
Timer input setup time
t
pcyc
indicates peripheral clock (Pφ) cycle.
PA27/A27/PINT3/DTEND3
PA24/A24/PINT0/DREQ3
PA26/A26/PINT2/DACT3
PA25/A25/PINT1/DACK3
PA31/CRx1/DTEND0
PA28/CTx0/DREQ0
PA29/CRx0/DACK0
PA30/CTx1/DACT0
PC25/IRQ3/SDA1
Symbol
t
t
t
TOCD
TICS
TCKS
PVCC
PVSS
VSS
Min.
20
20
Main Revisions for This Edition
56
55
54
53
52
51
50
49
48
47
46
45
0.1 F
Max.
100
PVCC
power supply
Page 1181 of 1190
Unit
ns
ns
ns
Figure
Figure 31.25
Figure 31.26