DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 138

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 5 Exception Handling
5.7.5
When an integer division instruction performs division by zero or the result of integer division
overflows, integer division instruction exception handling starts. The instructions that may become
the source of division-by-zero exception are DIVU and DIVS. The only source instruction of
overflow exception is DIVS, and overflow exception occurs only when the negative maximum
value is divided by −1. The CPU operates as follows:
1. The exception service routine start address which corresponds to the integer division exception
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
4. After jumping to the address fetched from the exception handling vector table, program
5.7.6
An FPU exception handling is generated when the V, Z, O, U or I bit in the FPU exception enable
field (Enable) of the floating point status/control register (FPSCR) is set. This indicates the
occurrence of an invalid operation exception defined by the IEEE standard 754, a division-by-zero
exception, overflow (in the case of an instruction for which this is possible), underflow (in the
case of an instruction for which this is possible), or inexact exception (in the case of an instruction
for which this is possible).
The floating-point operation instructions that may cause generation of an FPU exception handling
are FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS,
FCNVSD, and FSQRT.
An FPU exception handling is generated only when the corresponding FPU exception enable bit
(Enable) is set. When the FPU detects an exception source by a floating-point operation, FPU
operation is halted and FPU exception handling generation is reported to the CPU. When
exception handling is started, the CPU operations are as follows.
1. The start address of the exception service routine which corresponds to the FPU exception
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
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that occurred is fetched from the exception handling vector table.
integer division instruction at which the exception occurred.
execution starts. The jump that occurs is not a delayed branch.
handling that occurred is fetched from the exception handling vector table.
instruction to be executed after the last executed instruction.
Integer Division Exceptions
FPU Exceptions
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010