DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 177

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
6.7
Table 6.5 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception handling starts and fetching of the first instruction in the
interrupt exception service routine begins. The interrupt processing operations differ in the cases
when banking is disabled, when banking is enabled without register bank overflow, and when
banking is enabled with register bank overflow. Figures 6.4 and 6.5 show examples of pipeline
operation when banking is disabled. Figures 6.6 and 6.7 show examples of pipeline operation
when banking is enabled without register bank overflow. Figures 6.8 and 6.9 show examples of
pipeline operation when banking is enabled with register bank overflow.
Table 6.5
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Item
Time from occurrence of
interrupt request until interrupt
controller identifies priority,
compares it with mask bits in
SR, and sends interrupt request
signal to CPU
Time from
input of
interrupt
request
signal to
CPU until
sequence
currently
being
executed is
completed,
interrupt
exception
handling
starts, and
first
instruction in
interrupt
exception
service
routine is
fetched
Interrupt Response Time
No
register
banking
Register
banking
without
register
bank
overflow
Register
banking
with
register
bank
overflow
Interrupt Response Time
Min.
Max.
Min.
Max.
Min.
Max.
NMI
2 Icyc +
2 Bcyc +
1 Pcyc
3 Icyc + m1 + m2
4 Icyc + 2 (m1 + m2) + m3
⎯
⎯
⎯
⎯
User Break
3 Icyc
Number of States
H-UDI
2 Icyc +
1 Pcyc
3 Icyc + m1 + m2
12 Icyc + m1 + m2
3 Icyc + m1 + m2
3 Icyc + m1 + m2 + 19 (m4)
IRQ, PINT
2 Icyc +
3 Bcyc +
1 Pcyc
Peripheral
Module
2 Icyc +
1 Bcyc +
1 Pcyc
Section 6 Interrupt Controller (INTC)
Remarks
Min. is when the interrupt
wait time is zero.
Max. is when a higher-
priority interrupt request
has occurred during
interrupt exception
handling.
Min. is when the interrupt
wait time is zero.
Max. is when an interrupt
request has occurred
during execution of the
RESBANK instruction.
Min. is when the interrupt
wait time is zero.
Max. is when an interrupt
request has occurred
during execution of the
RESBANK instruction.
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