DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 187

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
6.9
Interrupt request signals can be used to activate the DMAC and transfer data.
Interrupt sources that are specified to activate the DMAC are masked by setting the DMA transfer
enable bit in DREQER0 to DREQER3 to 1 without being input to the INTC.
6.9.1
1. Clear the corresponding DMAC transfer request enable bit in DREQER0 to DREQER3 to 0.
2. When an interrupt occurs, the interrupt request will be sent to the CPU.
3. The CPU clears the interrupt source and performs the necessary processing in the interrupt
6.9.2
1. Select* the signals as DMAC activating sources by setting the corresponding DMAC transfer
2. When an interrupt occurs, the activation source will be sent to the DMAC.
3. The DMAC clears the activation source during the transfer.
Note: * As for the method to select the DMAC request sources, see section 11, Direct Memory
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
handling routine.
request enable bit in DREQER0 to DREQER3 to 1. This masks the CPU interrupt source
regardless of the interrupt priority register settings.
Data Transfer with Interrupt Request Signals
Handling Interrupt Request Signals as Sources for CPU Interrupt but not DMAC
Activation
Handling Interrupt Request Signals as Sources for DMAC Activation but not CPU
Interrupt
Access Controller (DMAC).
Section 6 Interrupt Controller (INTC)
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