DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 202
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 7 User Break Controller (UBC)
6. When selecting the I bus as the break condition, note as follows:
7.4.2
1. When C bus/instruction fetch/read/word or longword is set in the break bus cycle register
2. A break for instruction fetch which is set as a break before instruction execution occurs when it
3. When setting a break condition for break after instruction execution, the instruction set with
4. When an instruction fetch cycle is set, the break data register (BDR) is ignored. Therefore,
5. If the I bus is set for a break of an instruction fetch cycle, the setting is invalidated.
Page 174 of 1190
⎯ Whether or not the access the CPU issued on the C bus is issued on the I bus depends on
⎯ When a break condition is specified for the I bus, only the data access cycle is monitored.
⎯ If a break condition is specified for the I bus, even when the condition matches in an I bus
(BBR), the break condition is the FAB bus instruction fetch cycle. Whether a start of user
break interrupt exception processing is set before or after the execution of the instruction can
be selected with the PCB0 or PCB1 bit in the break control register (BRCR) for the
appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the
break address register (BAR) to 0. A break cannot be generated as long as this bit is set to 1.
is confirmed that the instruction has been fetched and will be executed. This means a break
does not occur for instructions fetched by overrun (instructions fetched at a branch or during
an interrupt transition, but not to be executed). When this kind of break is set for the delay slot
of a delayed branch instruction, the user break interrupt request is not received until the
execution of the first instruction at the branch destination.
the break condition is executed and then the break is generated prior to execution of the next
instruction. As with pre-execution breaks, a break does not occur with overrun fetch
instructions. When this kind of break is set for a delayed branch instruction and its delay slot,
the user break interrupt request is not received until the first instruction at the branch
destination.
break data cannot be set for the break of the instruction fetch cycle.
Note: If a branch does not occur at a delayed branch instruction, the subsequent instruction is
the setting of the cache. As regard to the I bus operation that depends on cache conditions,
see table 8.8 in section 8, Cache.
The instruction fetch cycle (including cache update cycle) is not monitored.
cycle resulting from an instruction executed by the CPU, at which instruction the break is
to be accepted cannot be clearly defined.
Break on Instruction Fetch Cycle
not recognized as a delay slot.
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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