DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 268

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Page 240 of 1190
CKIO
A27 to A0
CSn
RD
WR
D31 to D0
Note: * RD assert wait operation during the second and subsequent bus accesses differs depending on the page read
access mode setting value.
Ts
CS assert wait
RD assert wait
Tw1
Read cycle wait
Figure 9.4 Basic Bus Timing (Page Read Operation)
Bus access
A0
(first time)
Twn
Tend
(Trd)
RD assert wait*
Tn1 Tn2
and subsequent times)
Page read cycle wait
Bus access (second
A1
Twn
Tend
(Trd)
Tn1 Tn2
CS delay cycle during
cycle during read
read (end only)
CS delay
R01UH0026EJ0300 Rev. 3.00
Tnm
Start enable point
of next bus access
SH7201 Group
Sep 24, 2010