DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 327

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
The DMA controller (hereafter DMAC) is a module that handles high-speed data transfer without
CPU intervention in response to requests from software, on-chip peripheral I/O modules, or
external pins (external modules). The DMAC itself does not distinguish between requests from
on-chip peripheral I/O or external pins (external modules). The DMA supports data transfer
between memory units, memory and I/O modules, and I/O modules.
11.1
• Channel number: Up to eight channels (with four channels capable of external requests)
• Transfer requests: Requests from 37 sources including software trigger, on-chip peripheral I/O,
• Maximum transfer bytes: 64 Mbytes
• Address space: 4 Gbytes
• Transfer data sizes:
• Transfer mode:
• Maximum transfer speed:
• Transfer conditions:
• Channel priority:
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
and external pins (external modules)
⎯ Single data transfer: 8, 16, 32, 64, and 128 bits
⎯ Single operand transfer: 1, 2, 4, 8, 16, 32, 64, and 128 data
⎯ Non-stop transfer: Up to the byte count "0"
⎯ Cycle-stealing transfer (dual-address transfer)
⎯ Pipelined transfer (dual-address transfer)
⎯ Cycle-stealing transfer: Minimum of three clock cycles per unit data transfer
⎯ Pipelined transfer: Minimum of one clock cycle per unit data transfer
⎯ Unit operand transfer: a single sequence of single operand data transfer in response to a
⎯ Sequential operand transfer: single operand transfers are repeated until the byte count
⎯ Non-stop transfer: data is continuously transferred until the byte count reaches "0" in
Channel 0 > channel 1 > → > channel 6 > channel 7 (this priority order is fixed)
Section 11 Direct Memory Access Controller (DMAC)
DMA request
reaches "0"
response to a single DMA request
Features
Section 11 Direct Memory Access Controller (DMAC)
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