DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 365

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
Note: Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
31 to 24 DEDET
23 to 0
1, …, 24: channel 7).
Bit Name
⎯
Initial
Value
All 0
All 0
R/W
R/W
R
Description
Values read: DMA Transfer End Condition Detection
Values written: DMA Transfer End Condition
These bits are used to verify the status of DMA
transfer end condition detection for each channel.
Reading this register does not automatically clear the
bits. Once a bit has been set to "1", the value is
retained in the register as long as the bit is not cleared
by software or a reset.
•
•
When the DMA transfer end interrupt is in use and an
interrupt request generated for a given channel starts
to be handled, write a "1" to the corresponding DMA
transfer end condition detection (DEDET) bit.
When the DMA transfer end condition detection
(DEDET) bits are cleared to "0", the DMA interrupt
request status bit (DISTS) is also cleared.
Values read:
0: DMA transfer end condition not detected
1: DMA transfer end condition detected
Values written:
0: Invalid
1: Clears DMA transfer end condition detection and
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA interrupt request status
Condition for setting to "1"
When the DMA transfer end condition is detected,
these bits are set to "1".
Condition for clearing to "0"
These bits are cleared to "0" by writing a "1" to the
bits to be cleared. Write "0" to bits that are not to
be cleared. While a bit is clear, it cannot be set to
"1" by a write operation.
Section 11 Direct Memory Access Controller (DMAC)
Detection, DMA Interrupt Request
Status Clear
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