DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 370

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Direct Memory Access Controller (DMAC)
11.4.2
There are three methods of DMA transfer ⎯ the unit transfer operation, sequential operand
transfer, and non-stop transfer. These are selectable through the setting of the DMA transfer
condition selection bits (DSEL) in DMA Control Register A (DMCNTAn). Each of the conditions
is explained below. Table 11.5 and figure 11.3 are a list and chart of the DMA transfer conditions.
(1)
Setting the DMA transfer condition selection bits (DSEL) to 00 selects this mode. A single DMA
request initiates continuous transfer of the number of bytes selected by the OPSEL bits in the
DMA mode register. If the byte counter does not reach 0 in single operand transfer, the DMA
transfer is completed by repeating unit transfer operations until the byte counter does reach 0.
In the case that the DMA transfer condition is the unit operand transfer and the input sense mode
of DMA request is the level sense, there is the mask period of the DMA request in the channel
arbitration period after one operand transfer end (please refer to section 11.7.3, Sense Mode for
DMA Requests for details). Therefore, in the channel arbitration period after one operand transfer
end, in the case that there is no DMA request of the higher-priority channel than the transferring
channel and there is the DMA request of the lower-priority channel than the transferring channel,
the DMA transfer of the low-priority channel starts. To execute the DMA transfer of the high-
priority channel in succession, please set the DMA transfer condition to the sequential operand
transfer or the non-stop transfer.
(2)
Setting the DMA transfer condition selection bits (DSEL) to 01 selects this mode. A single DMA
request initiates transfer in units of the number of bytes selected by the OPSEL bits in the DMA
mode register (i.e., unit transfer operations) until the DMA transfer is complete (i.e., until the byte
counter reaches zero). Channel arbitration is performed on completion of each unit transfer
operation. Transfer on the channel for the sequential operand transfer automatically resumes
unless there is a DMA request from a higher-priority channel.
In the case that the DMA transfer condition is the sequential operand transfer, even if the input
sense mode of DMA request is the level sense, there is no mask period before the byte count
becomes 0. Therefore, the DMA transfer of the low-priority channel than the transferring channel
cannot start.
Page 342 of 1190
Unit Operand Transfer
Sequential Operand Transfer
DMA Transfer Condition
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010