DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 376

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Direct Memory Access Controller (DMAC)
Note:
11.5.2
The DMAC generates two types of interrupt request signal for the interrupt controller. One
consists of the interrupt request signals for the individual channels (DMINT_N) and the other is
the common interrupt request signal in which the interrupt request signals from all channels are
pooled to produce a common interrupt request signal (DMINTA_N).
Figure 11.4 is a block diagram showing how the per-channel and common interrupt requests are
generated.
When a DMA transfer ends and the DMA interrupt control bit (DINTM) for the corresponding
channel in the DMA interrupt control register (DMICNT) is set to "1", interrupt requests for the
corresponding channel are generated.
Only those channels for which the DMA common interrupt request signal control bit (DINTA) in
the DMA common interrupt control register (DMICNTA) is set to "1" contribute to the output of
common interrupt request.
Once generated, an interrupt request is cleared to "0" by writing a "1" to the corresponding DMA
transfer end condition detection bit (DEDET).
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If the DMA byte count reload function enable bit (BRLOD) in the DMA control register A
(DMCNTAn) is set to "1", the DMA current byte count register (DMCBCTn) is reloaded with
the value in the DMA reload byte count register (DMRBCTn).
If reloading is not to be executed, set ECLR = "1" to ensure that the DEN bit is cleared.
DMA Interrupt Requests
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010