DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 58

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 2 CPU
2.3.2
Addressing modes and effective address calculation are as follows:
Table 2.8
Page 30 of 1190
Addressing Mode Instruction Format
Register direct
Register indirect
Register indirect
with post-increment
Register indirect
with pre-decrement
Addressing Modes
Addressing Modes and Effective Addresses
Rn
@Rn
@Rn+
@-Rn
Effective Address Calculation
The effective address is register Rn.
(The operand is the contents of register Rn.)
The effective address is the contents of register
Rn.
The effective address is the contents of register
Rn. A constant is added to the contents of Rn
after the instruction is executed. 1 is added for a
byte operation, 2 for a word operation, and 4 for
a longword operation.
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted
for a byte operation, 2 for a word operation, and
4 for a longword operation.
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn – 1/2/4
+
–
Rn – 1/2/4
Rn
Rn
R01UH0026EJ0300 Rev. 3.00
Equation
—
Rn
Rn
(After instruction
execution)
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)
SH7201 Group
Sep 24, 2010