DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 632

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 13 8-Bit Timers (TMR)
Note:
Page 604 of 1190
Bit
5
4, 3
2 to 0
* To use an external reset or external clock, the function of the corresponding pin should
Bit Name
OVIE
CCLR[1:0]
CKS[2:0]
be selected using the pin function controller (PFC). For details, see section 23, Pin
Function Controller (PFC).
Initial
Value
0
00
000
R/W
R/W
R/W
R/W
Description
Timer Overflow Interrupt Enable
Selects whether OVF interrupt requests (OVI) are
enabled or disabled when the OVF flag in TCSR is set
to 1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
Counter Clear 1 and 0*
These bits select the method by which TCNT is
cleared.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared at rising edge (TMRIS in TCCR is cleared
Clock Select 2 to 0*
These bits select the clock input to TCNT and count
condition. See table 13.2.
to 0) of the external reset input or when the external
reset input is high (TMRIS in TCCR is set to 1)
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010