DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 686

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 15 Realtime Clock (RTC)
Page 658 of 1190
Bit
4
3
2, 1
0
Bit Name
CIE
AIE
—
AF
Initial
Value
0
0
All 0
0
R/W
R/W
R/W
R
R/W
Description
Carry Interrupt Enable Flag
When the carry flag (CF) is set to 1, the CIE bit enables
interrupts.
0: A carry interrupt is not generated when the CF flag is
1: A carry interrupt is generated when the CF flag is set
Alarm Interrupt Enable Flag
When the alarm flag (AF) is set to 1, the AIE bit allows
interrupts.
0: An alarm interrupt is not generated when the AF flag
1: An alarm interrupt is generated when the AF flag is
Reserved
These bits are always read as 0. The write value should
always be 0.
Alarm Flag
The AF flag is set when the alarm time, which is set by
an alarm register (ENB bit in RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, RMONAR, or RYRAR is
set to 1), and counter match.
0: Alarm register and counter not match
[Clearing condition]
•
1: Alarm register and counter match *
[Setting condition]
•
Note:
set to 1
to 1
is set to 1
set to 1
When 0 is written to AF.
When alarm register (only a register with ENB bit
set to 1) and counter match
* Writing 1 holds previous value.
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010