DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 751

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
In serial reception, the SCIF operates as described below.
1. The SCIF synchronizes with serial clock input or output and starts the reception.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR,
Figure 16.15 shows an example of SCIF receive operation.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the RDF flag is set to 1 and the SCIF stores the received data in SCFRDR. If
the check is not passed (overrun error is detected), further reception is prevented.
the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the
receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE) in
SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).
Serial clock
Serial data
RDF
ORER
Figure 16.15 Example of SCIF Receive Operation
RXI
interrupt
request
Bit 7
LSB
Data read from SCFRDR and
RDF flag cleared to 0 by RXI
interrupt handler
Bit 0
One frame
Bit 7
MSB
Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 0
RXI
interrupt
request
Bit 1
Bit 6
BRI interrupt request
by overrun error
Bit 7
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