DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 790

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 17 I
17.4.8
Flowcharts in respective modes that use the I
17.21.
Page 762 of 1190
No
No
No
No
No
No
Write 1 to BBSY and 0 to SCP
Example of Use
2
Write transmit data in ICDRT
Write transmit data in ICDRT
Write transmit data in ICDRT
C Bus Interface 3 (IIC3)
Write 0 to BBSY and SCP
Read ACKBR in ICIER
Read BBSY in ICCR2
Read TEND in ICSR
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Clear TDRE in ICSR
Set MST and TRS
Set MST and TRS
in ICCR1 to 1
in ICCR1 to 0
ACKBR=0 ?
BBSY=0 ?
TEND=1 ?
TDRE=1 ?
Last byte?
TEND=1 ?
STOP=1 ?
Transmit
Initialize
Figure 17.18 Sample Flowchart for Master Transmit Mode
mode?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Master receive mode
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Wait for last byte to be transmitted.
[11] Clear the TEND flag.
[12] Clear the STOP flag.
[13] Issue the stop condition.
[14] Wait for the creation of stop condition.
[15] Set slave receive mode. Clear TDRE.
Test the status of the SCL and SDA lines.
Set master transmit mode.
Issue the start condition.
Set the first byte (slave address + R/W) of transmit data.
Wait for 1 byte to be transmitted.
Test the acknowledge transferred from the specified slave device.
Set the second and subsequent bytes (except for the final byte) of transmit data.
Wait for ICDRT empty.
Set the last byte of transmit data.
2
C bus interface 3 are shown in figures 17.18 to
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010