DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 824

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 18 Serial Sound Interface (SSI)
(7)
Several more configuration bits in non-compressed mode are shown below. These bits are not
mutually exclusive, but some combinations may not be useful for any other device.
These configuration bits are described below with reference to figure 18.10, Basic Sample Format.
Page 796 of 1190
SWL = 6 bits (not attainable in SSI module, demonstration only)
DWL = 4 bits (not attainable in SSI module, demonstration only)
CHNL = 00, SCKP = 0, SWSP = 0, SPDP = 0, SDTA = 0, PDTA = 0, DEL = 0, MUEN = 0
4-bit data samples continuously written to SSITDR are transmitted onto the serial audio bus.
SSISCK
SSIWS
SSIDATA
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 11, SPDP = 0, SDTA = 1
System word length = data word length × 4
SSISCK
SSIWS
SSIDATA
Bit Setting Configuration Format
Figure 18.9 Multichannel Format (8 Channels; Transmitting and Receiving in
Key for this and following diagrams:
TD28
TDn
0
1
(Transmit Mode with Example System/Data Word Length)
MSB
the order of Padding Bits and Serial Data; with Padding)
word 1
0
Data
Arrow head indicates sampling point of receiver
Bit n in SSITDR
means a low level on the serial bus (padding or mute)
means a high level on the serial bus (padding)
LSB
0
MSB
word 2
TD31 TD30 TD29 TD28
System word 1
Data
Figure 18.10 Basic Sample Format
1st channel
LSB MSB
word 3
Data
LSB MSB
word 4
Data
LSB
0
0
MSB
word 5
Data
TD31 TD30 TD29 TD28
LSB MSB
2nd channel
word 6
Data
System word 2
LSB MSB
word 7
R01UH0026EJ0300 Rev. 3.00
Data
LSB MSB
0
word 8
Data
0
SH7201 Group
LSB
Sep 24, 2010
TD31