DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 868

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 19 Controller Area Network (RCAN-ET)
Bit 12 – Bus Activity while in Sleep Mode (IRR12): IRR12 indicates that a CAN bus activity is
present. While the RCAN-ET is in sleep mode and a dominant bit is detected on the CAN bus, this
bit is set. This interrupt is cleared by writing a '1' to this bit position. Writing a '0' has no effect. If
auto wakeup is not used and this interrupt is not requested it needs to be disabled by the related
interrupt mask register. If auto wake up is not used and this interrupt is requested it should be
cleared only after recovering from sleep mode. This is to avoid that a new falling edge of the
reception line causes the interrupt to get set again.
Please note that the setting time of this interrupt is different from the clearing time of GSR4.
Bits 11 to 10: Reserved
Bit 9 – Message Overrun/Overwrite Interrupt Flag (IRR9): Flag indicating that a message has
been received but the existing message in the matching Mailbox has not been read as the
corresponding RXPR or RFPR is already set to '1' and not yet cleared by the CPU. The received
message is either abandoned (overrun) or overwritten dependant upon the NMC (New Message
Control) bit. This bit is cleared when
(by writing '1') or by setting MBIMR (MailBox interrupt Mast Register) for all UMSR flag set
cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit position
has no effect.
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Bit 12: IRR12
0
1
Bit 9: IRR9
0
1
Description
bus idle state (Initial value)
[Clearing condition] Writing 1
CAN bus activity detected in RCAN-ET sleep mode
[Setting condition] dominant bit level detection on the CRx line while in sleep
mode
Description
No pending notification of message overrun/overwrite
[Clearing condition] Clearing of all bit in UMSR/setting MBIMR for all UMSR
set (initial value)
A receive message has been discarded due to overrun condition or a
message has been overwritten
[Setting condition] Message is received while the corresponding RXPR
and/or RFPR = 1 and MBIMR = 0
all bit in UMSR
(Unread Message Status Register)
R01UH0026EJ0300 Rev. 3.00
. It is also
SH7201 Group
are cleared
Sep 24, 2010