DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 895

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
19.6.4
The diagram below shows the message receive sequence.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Notes: 1. Only if CPU clears RXPR[N]/RFPR[N] at the same time that UMSR is set in overrun, RXPR[N]/RFPR[N] may be set again even thuotgh
CAN Bus
RCAN-ET
Loop (n = 15; n
Store Message by Overwriting
Set UMSR
Set IRR9 (if MBIMR[N] = 0)
Generate Interrupt Signal
Set RXPR[N] (RFPR[N])
Set IRR1 (IRR2) (if MBIMR[N] = 0)
Generate Interrupt Signal
(if IMR9 = 0)
(if IMR1 (IMR2) = 0)
(if MBC is config to receive)
Store Mailbox-Number[N]
and go back to idle state
Valid CAN-ID Received
ID Matched?
Mailbox[N] + LAFM[N]
2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N]
Compare ID with
Intrrupt signal
the message has not been updated.
cleared and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/
RFPR[N]/UMSR[N] when UMSR[N] = 1 and consider the message obsolate.
Message Receive Sequence
Yes
Yes
0; n = n - 1)
No
End Of Arbitration Field
OverWrite
N = 0?
(if IMR9 = 0)
Reject Message
Set UMSR
Set IRR9 (if MBIMR[N] = 0)
Generate Interrupt Signal
Set RXPR[N] (RFPR[N])
n = n - 1
No
Intrrupt signal
Figure 19.11 Message receive sequence
Yes
IDLE
CPU received interrupt due to CAN Message Reception
OverRun
*
Valid CAN Frame Received
1
Already Set?
OverWrite or
(RFPR[N])
OverRun?
Set RXPR[N] (RFPR[N])
Set IRR1 (IRR2) (if MBIMR[N] = 0)
Generate Interrupt Signal
End Of Frame
(if IMR1 (IMR2) = 0)
RXPR[N]
Store Message
(NMC)
MSG
Yes
Intrrupt signal
No
Section 19 Controller Area Network (RCAN-ET)
Write 1 to RXPR[N]
Read RXPR[N] = 1
Read Mailbox[N]
Clear by clear
UMSR[N]
Read IRR
IRR[1]
set?
Yes
Exit Interrpt Service
*
2
Routine
No
Write 1 to RFPR[N]
Read RFPR[N] = 1
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Read Mailbox[N]
Clear by clear
UMSR[N]
*
2