DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 935

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
21.4
The D/A converter includes D/A conversion circuits for two channels, each of which can operate
independently. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and the
conversion result is output.
An operation example of D/A conversion on channel 0 is shown below. Figure 21.2 shows the
timing of this operation.
1. Write the conversion data to DADR0.
2. Set the DAOE0 bit in DACR to 1 to start D/A conversion. The conversion result is output from
3. If DADR0 is written to again, the conversion is immediately started. The conversion result is
4. If the DAOE0 bit is cleared to 0, analog output is disabled.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
the analog output pin DA0 after the conversion time t
continues to be output until DADR0 is written to again or the DAOE0 bit is cleared to 0. The
output value is expressed by the following formula:
output after the conversion time t
Contents of DADR
Operation
[Legend]
t
φ
Address
DADR0
DAOE0
DA0
DCONV
256
: D/A conversion time
High-impedance state
DADR0
write cycle
Figure 21.2 Example of D/A Converter Operation
× AVref
DACR
write cycle
DCONV
Conversion data 1
t
DCONV
has elapsed.
Conversion
result 1
DADR0
write cycle
DCONV
t
has elapsed. The conversion result
DCONV
Conversion data 2
Conversion
result 2
Section 21 D/A Converter (DAC)
DACR
write cycle
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