DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 96

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 3 Floating-Point Unit (FPU)
3.3.2
FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and
selects the rounding mode.
Page 68 of 1190
Bit
31 to 23
22
21
20
19
18
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Floating-Point Status/Control Register (FPSCR)
Bit Name
—
QIS
—
SZ
PR
DN
R/W
31
15
R
0
0
R/W
30
14
R
0
0
Cause
R/W
29
13
R
0
0
Initial
Value
All 0
0
0
0
0
1
R/W
28
12
R
0
0
R/W
27
11
R
0
0
R/W
R
R/W
R
R/W
R/W
R
R/W
26
10
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Nonnunerical Processing Mode
0: Processes qNaN or ±∞ as such
1: Treats qNaN or ±∞ as the same as sNaN (valid only
Reserved
This bit is always read as 0. The write value should
always be 0.
Transfer Size Mode
0: Data size of FMOV instruction is 32-bits
1: Data size of FMOV instruction is a 32-bit register
Precision Mode
0: Floating-point instructions are executed as
1: Floating-point instructions are executed as
Denormalization Mode (Always fixed to 1 in SH2A-
FPU)
1: Denormalized number is treated as zero
Enable
R/W
when the V bit in FPSCR enable is set to 1)
25
pair (64 bits)
single-precision operations
double-precision operations (graphics support
instructions are undefined)
R
0
9
0
R/W
24
R
0
8
0
R/W
23
R
0
7
0
R/W
R/W
QIS
22
6
0
0
R/W
21
R
0
5
0
Flag
R/W
R/W
SZ
20
0
4
0
R01UH0026EJ0300 Rev. 3.00
R/W
R/W
PR
19
0
3
0
R/W
DN
18
R
1
2
0
SH7201 Group
RM1
R/W
R/W
Sep 24, 2010
17
0
1
0
Cause
RM0
R/W
R/W
16
0
0
1