HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 435
HD6417727BP160CV
Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP160CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
HD6417727BP160CV
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13.2.5
USB Host issues 1 to 4 burst request to LBSC as normal read or write action. Since the burst
length issued by USB Host is occasionally changed as FIFO pointer rises up or falls, it is not
supposed as 4 burst exactly.
13.2.6
This LSI has five types of bus master: CPU, DMAC and Refresh (BSC system), and LCDC and
USBH (LBSC system). The following priority order is set for these buses.
1. The BSC and LBSC systems are the same in priority level.
2. In the BSC system, Refresh has the highest priority.
3. Between CPU and DMAC, DMAC is higher in priority when DMA burst setting is made. In
4. LCDC and USBH are the same priority level in the LBSC system.
In cycle steal, the priority level of DMA transfer is very low. Therefore, if the DMAC transfer
speed may cause problems, it is recommended to use the level-input burst transfer setting for
DMAC, especially when DREQ signals from an external device can be negated.
cycle steal, CPU and DMAC are the same in priority level.
Synchronous
(Area 3)
DRAM
USBH Li Bus Access
Setting of DMA Transfer with Bus Arbitration of Other Module
Figure 13.1 Block Diagram of Li Bus Architecture
Bus
LBSC
BSC
Bus arbitration
Rev.6.00 Mar. 27, 2009 Page 377 of 1036
Section 13 Li Bus State Controller (LBSC)
Li bus
REJ09B0254-0600
USBH
LCDC
SH7727
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