HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 443
HD6417727BP160CV
Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP160CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
HD6417727BP160CV
Manufacturer:
LITEON
Quantity:
46 000
Company:
Part Number:
HD6417727BP160CV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14.2.2
The DMA destination address registers 0 to 3 (DAR0 to DAR3) are 32-bit read/write registers that
specify the destination address of a DMA transfer. These registers include count functions, and
during a DMA transfer, these registers indicate the next destination address.
To transfer data in 16 bits or in 32 bits, specify the address on the 16-bit or 32-bit boundary.
When transferring data in 16-byte units, always set a value at a 16-byte boundary (16n address) as
the destination address. If any other address is specified, correct operation is not guaranteed.
Initial values are undefined after a reset. The previous value is held in standby mode.
Initial value:
Initial value:
DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)
R/W:
R/W:
Bit:
Bit:
R/W
R/W
31
23
—
—
R/W
R/W
30
22
—
—
R/W
R/W
29
21
—
—
Section 14 Direct Memory Access Controller (DMAC)
R/W
R/W
28
20
—
—
Rev.6.00 Mar. 27, 2009 Page 385 of 1036
R/W
27
—
R/W
26
…
—
…
…
…
REJ09B0254-0600
R/W
25
—
R/W
R/W
24
—
—
0
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