HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 509
HD6417727BP160CV
Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP160CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
HD6417727BP160CV
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Quantity:
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Part Number:
HD6417727BP160CV
Manufacturer:
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15.3
15.3.1
Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). The
TCNT is a down-counter. The auto-reload function can be used to enable synchronized counting
and counting by external events.
15.3.2
Counter Operation: When the STR0 to STR2 bits in the timer start register (TSTR) are set, the
corresponding timer counters (TCNT) start decrementation. When TCNT underflows, the UNF
flag in the corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR
is 1, an interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to
TCNT and the decrementation is continued.
The decrementation is set as follows (figure 15.2):
Note: When an interrupt has been generated, clear the flag in the interrupt handler that
TMU Operation
Overview
Basic Functions
caused it.
If interrupts are enabled without clearing the flag, another interrupt will be generated.
interrupt generation
Set timer constant
Select operation
Select counter
Set underflow
Initialize timer
Start counting
counter
register
clock
Figure 15.2 Setting the Count Operation
(1)
(2)
(3)
(4)
(5)
(1) Select the counter clock with the TPSC2
(2) Set whether or not an interrupt is
(3) Set a value in the timer constant register
(4) Set the initial value in the timer counter
(5) Set the STR bit in the timer start register
to TPSC0 bits in the timer control register
(TCR).
generated when TCNT underflows, with
the UNIE bit in TCR.
(TCOR) (the cycle is the set value plus 1).
(TCNT).
(TSTR) to 1 to start operation.
Rev.6.00 Mar. 27, 2009 Page 451 of 1036
Section 15 Timer (TMU)
REJ09B0254-0600
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