HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 525
HD6417727BP160CV
Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP160CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number:
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16.2.12 Day of the Week Alarm Register (RWKAR)
The day of the week alarm register (RWKAR) is an 8-bit read/write alarm register that
corresponds to the BCD-coded day of week section counter RWKCNT of the RTC. When the
ENB bit is set to 1in RWKAR, the RWKAR value and RWKCNT value are compared. In this
way, the RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR registers are
checked, and when the ENB bit is set to 1, the alarm register and the corresponding counter are
compared. If all values in the specified alarm registers and the corresponding counters match, an
RTC alarm interrupt is generated.
The settable range is “0 to 6 in decimal + ENB bit”. If other values are set, correct operation is not
provided.
Only the ENB bit in RWKAR is initialized to 0 by a power-on reset, and the other bits are not
initialized. The RWKAR contents are retained after a manual reset or in standby mode.
Days of the week are coded as shown in table 16.4.
Table 16.4 Day-of-Week Codes (RWKAR)
Day of Week
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
16.2.13 Date Alarm Register (RDAYAR)
The date alarm register (RDAYAR) is an 8-bit read/write alarm register that corresponds to the
BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit is set to 1in
RDAYAR, the RDAYAR value and RDAYCNT value are compared. In this way, the RSECAR,
Initial value:
R/W:
Bit:
ENB
R/W
7
0
—
R
6
0
—
R
5
0
Code
0
1
2
3
4
5
6
—
R
4
0
Rev.6.00 Mar. 27, 2009 Page 467 of 1036
—
R
3
0
Section 16 Realtime Clock (RTC)
R/W
—
2
Day of week
REJ09B0254-0600
R/W
—
1
R/W
—
0
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