DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 44
DF2552BR26DV
Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2552BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2552BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Table 5.9
Section 7 Bus Controller
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Section 8 Data Transfer Controller (DTC)
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Table 8.6
Table 8.7
Section 9 I/O Ports
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Rev. 6.00 Sep. 24, 2009 Page xlii of xlvi
REJ09B0099-0600
Interrupt Control Modes.......................................................................................... 100
Interrupts Selected in Each Interrupt Control Mode (1).......................................... 102
Interrupts Selected in Each Interrupt Control Mode (2).......................................... 102
Operations and Control Signal Functions in Each Interrupt Control Mode ............ 103
Interrupt Response Times (States) .......................................................................... 109
Number of States in Interrupt Handling Routine Execution Status......................... 110
Interrupt Source Selection and Clear Control ......................................................... 112
Pin Configuration .................................................................................................... 125
Bus Specifications for Each Area (Basic Bus Interface)......................................... 136
Data Buses Used and Valid Strobes ........................................................................ 146
Pin States in Idle Cycle ........................................................................................... 162
Pin States in Bus Mastership Released State........................................................... 163
Activation Source and DTCER Clearing ................................................................ 175
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................. 178
Register Function in Normal Mode......................................................................... 182
Register Function in Repeat Mode.......................................................................... 183
Register Function in Block Transfer Mode............................................................. 184
DTC Execution Status............................................................................................. 188
Number of States Required for Each Execution Status........................................... 188
Port Functions ......................................................................................................... 194
Input Pull-Up MOS States (Port A) ........................................................................ 232
Input Pull-Up MOS States (Port B)......................................................................... 238
Input Pull-Up MOS States (Port C)......................................................................... 242
Input Pull-Up MOS States (Port D) ........................................................................ 246
Input Pull-Up MOS States (Port E)......................................................................... 250
Examples of Ways to Handle Unused Input Pins.................................................... 265
TPU Functions ........................................................................................................ 268
TPU Pins ................................................................................................................. 271
CCLR0 to CCLR2 (channels 0 and 3)..................................................................... 277
CCLR0 to CCLR2 (channels 1, 2, 4, and 5)............................................................ 277
TPSC0 to TPSC2 (channel 0).................................................................................. 278
TPSC0 to TPSC2 (channel 1).................................................................................. 278
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