DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 504
DF2552BR26DV
Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2552BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2552BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 13 Serial Communication Interface (SCI)
• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but
Note: etu: Elementary time unit (time for transfer of 1 bit)
13.7.4
In Smart Card interface mode an internal clock generated by the on-chip baud rate generator can
only be used as a transmission/reception clock. In this mode, the SCI operates on a basic clock
with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed to 16 times in normal
asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the
falling edge of the start bit using the basic clock, and performs internal synchronization. As shown
in figure 13.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th
pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given
by the following formula.
Where M: Reception margin (%)
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
Rev. 6.00 Sep. 24, 2009 Page 456 of 928
REJ09B0099-0600
since error signal transfer is not performed, this flag is always cleared to 0.
M = | (0.5 –
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
M
Receive Data Sampling Timing and Reception Margin
= (0.5 – 1/2 × 372) × 100%
= 49.866%
2N
1
) – (L – 0.5) F –
| D – 0.5 |
N
(1 + F) | × 100
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