DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 511
DF2552BR26DV
Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2552BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
DF2552BR26DV
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When turning on the power or switching between Smart Card interface mode and software
standby mode, the following procedures should be followed in order to maintain the clock duty.
Powering On: To secure clock duty from power-on, the following switching procedure should be
followed.
When Changing from Smart Card Interface Mode to Software Standby Mode:
When Returning to Smart Card Interface Mode from Software Standby Mode:
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin
2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
3. Write 0 to the CKE0 bit in SCR to halt the clock.
4. Wait for one serial clock period.
5. Make the transition to the software standby state.
1. Exit the software standby state.
2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
CKE0
SCK
resistor to fix the potential.
to the value for the fixed output state in software standby mode.
operation. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
During this interval, clock output is fixed at the specified level, with the duty preserved.
normal duty.
Figure 13.31 Timing for Fixing Clock Output Level
Specified pulse width
Section 13 Serial Communication Interface (SCI)
Rev. 6.00 Sep. 24, 2009 Page 463 of 928
Specified pulse width
REJ09B0099-0600
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