DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 512
DF2552BR26DV
Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2552BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Quantity
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Part Number:
DF2552BR26DV
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Section 13 Serial Communication Interface (SCI)
13.8
13.8.1
Table 13.12 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
perform data transfer. The TDRE flag is cleared to 0 automatically when data is transferred by the
DTC*.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt
request can activate the DTC to transfer data. The RDRF flag is cleared to 0 automatically when
data is transferred by the DTC*.
A TEI interrupt is requested when the TEND flag is set to 1 and the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, if the TDRE and TEND flags are cleared simultaneously by the TXI
interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Note: * Flags are cleared only when the DISEL bit in DTC is 0 with the transfer couter other
Rev. 6.00 Sep. 24, 2009 Page 464 of 928
REJ09B0099-0600
Interrupt Sources
Interrupts in Normal Serial Communication Interface Mode
than 0.
Figure 13.32 Clock Halt and Restart Procedure
Normal operation
Software
standby
Normal operation
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