DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 547
DF2552BR26DV
Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2552BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2552BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, see figures
14.11 and 14.12. Since a flag may be set according to the port state, initialization should be
performed after all bits in ICSR have been cleared. The reception procedure and operations in
slave receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
2. When the slave address matches in the first frame following detection of the start condition,
(Master output)
(Master output)
(Slave output)
(Slave output)
processing
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
ICDRT
ICDRS
ICDRR
TDRE
TEND
SCL
SDA
SCL
SDA
User
TRS
Slave Receive Operation
Figure 14.10 Slave Transmit Mode Operation Timing (2)
9
A
Bit 7
1
Bit 6
2
Bit 5
3
Data n
Bit 4
[3] Clear TEND
4
Bit 3
5
Bit 2
6
[4] Read ICDRR (dummy read)
Bit 1
Rev. 6.00 Sep. 24, 2009 Page 499 of 928
Slave transmit mode
after clearing TRS
7
Section 14 I
Bit 0
8
9
A
2
C Bus Interface 2 (IIC2)
REJ09B0099-0600
[5] Clear TDRE
Slave receive
mode
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