DF2339EVFC25 Renesas Electronics America, DF2339EVFC25 Datasheet - Page 229
DF2339EVFC25
Manufacturer Part Number
DF2339EVFC25
Description
IC H8S MCU FLASH 384K 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2339EVFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2339EVFC25
HD64F2339EVFC25
HD64F2339EVFC25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2339EVFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2.2.59 (4)
SHLL (SHift Logical Left)
Operation
Rd (left logical shift)
Assembly-Language Format
SHLL.W #2, Rd
Operand Size
Word
Description
This instruction shifts the bits in a 16-bit register Rd (destination operand) two bits to the left. Bit
14 shifts into the carry flag. Bits 0 and 1 are cleared to 0.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Notes
The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.
Register direct
Addressing
Mode
SHLL (W)
Mnemonic
SHLL.W
C
Rd
MSB
Operands
b15
#2, Rd
b14
1st byte
1
. . . .
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 14.
2nd byte
5
Instruction Format
cleared to 0.
cleared to 0.
Rev. 4.00 Feb 24, 2006 page 213 of 322
—
I
rd
UI H
—
b1
0
Section 2 Instruction Descriptions
—
3rd byte
LSB
b0
0
—
U
N
0
4th byte
REJ09B0139-0400
Z
Shift Logical
V
0
States
No. of
C
1
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