HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 118
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 2 CPU
Table 2.16 Single Data Transfer Instruction Formats
Single
data
transfer
Note: * Codes reserved for system use.
Parallel Processing Instructions: Parallel processing instructions are provided for efficient
execution of digital signal processing using the DSP unit. They are 32 bits long and allow four
simultaneous processes, an ALU operation, multiplication, and two data transfers.
Parallel processing instructions are divided into an A field and a B field. The A field defines data
transfer instructions and the B field an ALU operation instruction and multiply instruction. These
instructions can be defined independently, and the processing is executed in parallel,
independently and simultaneously. A-field parallel data transfer instructions are shown in table
2.17, and B-field ALU operation instructions and multiply instructions in table 2.18.
Rev.6.00 Mar. 27, 2009 Page 60 of 1036
REJ09B0254-0600
Type
MOVS.W @-As,Ds
MOVS.W @As,Ds
MOVS.W @As+,Ds
MOVS.W @As+Is,Ds
MOVS.W Ds,@-As
MOVS.W Ds,@As
MOVS.W Ds,@As+
MOVS.W Ds,@As+Is
MOVS.L @-As,Ds
MOVS.L @As,Ds
MOVS.L @As+,Ds
MOVS.L @As+Is,Ds
MOVS.L Ds,@-As
MOVS.L Ds,@As
MOVS.L Ds,@As+
MOVS.L Ds,@As+Is
Mnemonic
15 14 13 12 11 10 9
1
1
1
1
0
1
0:R4
1:R5
2:R2
3:R3
As
8
7
Ds 0:(*)
6
1:(*)
2:(*)
3:(*)
4:(*)
5:A1
6:(*)
7:A0
8:X0
9:X1
A:Y0
B:Y1
C:M0
D:A1G
E:M1
F:A0G
5
4
3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
1
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