HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 209
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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cache will not function correctly. When modifying the LRU bits by software, set one of the
patterns listed in table 5.2.
The LRU bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
Table 5.2
LRU (5–0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
5.1.3
Table 5.3 shows details of the cache control register.
Table 5.3
Register
Cache control register
Cache control register 2
Note: * When address translation by the MMU does not apply, the address in parentheses should
5.2
5.2.1
The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also
has a CF bit (which invalidates all cache entries), and a WT and CB bits (which select either write-
through mode or write-back mode). Programs that change the contents of the CCR register should
be placed in address space that is not cached. Figure 5.2 shows the configuration of the CCR
register.
be used.
Register Configuration
Register Description
Cache Control Register (CCR)
LRU and Way Replacement
Register Configuration
Abbr.
CCR
CCR2
R/W
R/W
W
Size
Longword
Longword
Rev.6.00 Mar. 27, 2009 Page 151 of 1036
Way to be Replaced
3
2
1
0
Initial Value
H'00000000
H’00000000
REJ09B0254-0600
Section 5 Cache
Address
H'FFFFFFEC
H'040000B0
(H'A40000B0)*
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