HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 306
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 9 Power-Down Modes and Software Reset
Bit
MSTP17
MSTP15
MSTP14
MSTP13
MSTP11
MSTP10
MSTP9
MSTP8
MSTP7
MSTP6
MSTP5
MSTP4
MSTP2
MSTP1
MSTP0
Notes: 1. The initialized registers are the same as in the standby mode (see table 9.4).
Rev.6.00 Mar. 27, 2009 Page 248 of 1036
REJ09B0254-0600
2. The counter runs.
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
SIOF runs.
Clock supply to SIOF halted.
AFEIF runs.
Clock supply to AFEIF halted.
USBF runs.
Clock supply to USBF halted.
USBH runs.
Clock supply to USBH halted.
This bit should not be set to 1 when MSTP14 (bit 4) is 0.
LCDC runs.
Clock supply to LCDC halted.
PCC runs.
Clock supply to PCC halted.
X/Y memory runs.
Clock supply to X/Y memory halted.
UBC runs.
Clock supply to UBC halted.
DMAC runs.
Clock supply to DMAC halted.
DAC runs.
Clock supply to DAC halted.
ADC runs.
Clock supply to ADC halted, and all registers initialized.
SCIF runs.
Clock supply to SCIF halted.
TMU runs.
Clock supply to TMU halted. *
RTC runs.
Clock supply to RTC halted. Register access prohibited. *
SCI runs.
Clock supply to SCI halted.
1
2
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