HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 355
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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12.2.2
The bus control register 2 (BCR2) is a 16-bit read/write register that selects the bus-size width of
each area. It is initialized to H'3FF0 by a power-on reset, but is not initialized by a manual reset or
by standby mode. Do not access external memory outside area 0 until BCR2 register initialization
is complete.
Bits 15, 14, 3, 2, 1, and 0—Reserved: These bits are always read as 0. The write value should
always be 0.
Bits 2n + 1, 2n—Area n (2 to 6) Bus Size Specification (AnSZ1, AnSZ0): Specify the bus sizes
of physical space area n (n = 2 to 6).
Bit 2n + 1: AnSZ1
0
1
0
1
Initial value:
R/W:
Bit:
Bus Control Register 2 (BCR2)
15
—
R
0
14
—
R
0
Bit 2n: AnSZ0
0
1
0
1
0
1
0
1
R/W
SZ1
A6
13
1
R/W
SZ0
A6
12
1
R/W
SZ1
A5
11
1
R/W
SZ0
A5
10
1
Port A / B
Unused
Used
R/W
SZ1
A4
9
1
R/W
SZ0
A4
8
1
Rev.6.00 Mar. 27, 2009 Page 297 of 1036
R/W
SZ1
A3
7
1
Section 12 Bus State Controller (BSC)
R/W
SZ0
A3
6
1
Description
Reserved (Setting disabled)
Byte (8-bit) size
Word (16-bit) size
Longword (32-bit) size
Reserved (Setting disabled)
Byte (8-bit) size
Word (16-bit) size
Reserved (Setting disabled)
R/W
SZ1
A2
5
1
R/W
SZ0
A2
4
1
—
R
3
0
REJ09B0254-0600
—
R
2
0
—
R
1
0
—
R
0
0
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