HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 547

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

17.2.5
The serial mode register (SCSMR) is an eight-bit register that specifies the SCI serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write the SCSMR.
The SCSMR is initialized to H'00 by a reset or in standby and module standby modes.
Bit 7—Communication Mode (C/A): Selects whether the SCI operates in the asynchronous or
clock synchronous mode.
Bit 7: C/A
0
1
Bit 6—Character Length (CHR): Selects seven-bit or eight-bit data in the asynchronous mode.
In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 6: CHR
0
1
Note: * When seven-bit data is selected, the MSB (bit 7) of the transmit data register is not
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in the asynchronous mode. In the clock synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
Initial value:
transmitted.
Serial Mode Register (SCSMR)
R/W:
Bit:
Description
Asynchronous mode
Clock synchronous mode
Description
Eight-bit data
Seven-bit data*
R/W
C/A
7
0
CHR
R/W
6
0
R/W
PE
5
0
Section 17 Serial Communication Interface (SCI)
R/W
O/E
4
0
Rev.6.00 Mar. 27, 2009 Page 489 of 1036
STOP
R/W
3
0
R/W
MP
2
0
REJ09B0254-0600
CKS1
R/W
1
0
(Initial value)
(Initial value)
CKS0
R/W
0
0