HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 596
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 17 Serial Communication Interface (SCI)
17.4
The SCI has four interrupt sources in each channel: Transmit-end (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty (TXI). Table 17.13 lists the interrupt sources and
indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE
bits in the serial control register (SCSCR). Each interrupt request is sent separately to the interrupt
controller.
TXI is requested when the TDRE bit in the SCSSR is set to 1.
RXI is requested when the RDRF bit in the SCSSR is set to 1.
ERI is requested when the ORER, PER, or FER bit in the SCSSR is set to 1.
TEI is requested when the TEND bit in the SCSSR is set to 1. Where the TXI interrupt indicates
that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is
complete.
Table 17.13 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
See section 4, Exception Handling, for information on the priority order and relationship to non-
SCI interrupts.
Rev.6.00 Mar. 27, 2009 Page 538 of 1036
REJ09B0254-0600
SCI Interrupt Sources
Description
Receive error (ORER, PER, or FER)
Receive data full (RDRF)
Transmit data empty (TDRE)
Transmit end (TEND)
Priority When Reset Is Cleared
High
Low
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