HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 793

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

24.2.4
HcInterruptStatus Register (H'0400040C)
This register indicates the status in various events that cause hardware interrupts. When an event
occurs, the host controller sets the corresponding bit in this register. When the bit is set to 1, a
hardware interrupt is generated while an interrupt is enabled and the MsterInterrupEnable bit is set
in the HcInterruptEnable register (see section 24.2.5, HcInterruptEnable). The host control driver
clears a specified bit in this register by writing 1 in the bit position to be cleared. The host
controller driver cannot set any bit of these bits. The host controller never clears bits.
Register: HcInterruptStatus
Bits
31
30
29–7
6
5
HcInterruptStatus
Reset
0h
0b
0h
0b
0b
R/W
—
R/W
—
R/W
R/W
Offset: 0C–0F
Description
Reserved.
OwnershipChange (OC)
This bit is set by the host controller when the
OwnershipChangeRequest bit in the HcCommandStatus
reigster is set. This event generates a system management
interrupt at once when not masked.
When there is no SMI pin, this bit is set to 0.
0: The OCR bit in the HcCommandStatus register is not set.
1: The OCR bit in the HcCommandStatus register is set.
Reserved.
RootHubStatusChange (RHSC)
This bit is set when the content of HcRhStatus or the content of
any HcRhPortStatus 1, 2 register [Number of Downstream Port]
has changed.
0: The content of the HcRhStatus register or HcRhPortStatus
1: The content of the HcRhStatus register or HcRhPortStatus
FrameNumberOverflow (FNO)
This bit is set when MSB (bit 15) in the HcFumnumber register
changes value from 0 to 1 or from 1 to 0 or the
HccaFrameNumber bit is updated.
0: MSB or the HccaFrameNumber bit in the HcFmNumber
1: MSB or the HccaFrameNumber bit in the HcFmNumber
(initial value)
register is not changed. (initial value)
register is changed.
register is not updated. (initial value)
register is updated.
Rev.6.00 Mar. 27, 2009 Page 735 of 1036
Section 24 USB HOST Module
REJ09B0254-0600