HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 109

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
28
27 to 10 ⎯
9
8
7 to 4
3, 2
1
Bit Name
BL
M
Q
I3 to I0
⎯
S
Initial
Value
1
All 0
⎯
⎯
All 1
All 0
⎯
R/W
R/W
R
R/W
R/W
R/W
R
R/W
Description
Specifies whether an exception, interrupt, or user
break is enabled or not.
0: Enables an exception, interrupt, or user break.
1: Disables an exception, interrupt, or user break.
The BL bit is set to 1 in reset or exception handling
state.
These bits are always read as 0. The write value
should always be 0.
M Bit
Q Bit
These bits are used by the DIV0S, DIV0U, and DIV1
instructions. These bits can be changed even in user
mode by using the DIV0S, DIV0U, and DIV1
instructions. These bits are undefined at reset. These
bits do not change in an exception handling state.
Interrupt Mask
Indicates the interrupt mask level. These bits do not
change even if an interrupt occurs. At reset, these bits
are initialized to B'1111. These bits are not affected in
an exception handling state.
These bits are always read as 0. The write value
should always be 0.
Saturation Mode
Specifies the saturation mode for multiply instructions
or multiply and accumulate instructions. This bit can be
specified by the SETS and CLRS instructions in user
mode.
At reset, this bit is undefined. This bit is not affected in
an exception handling state.
Block
Reserved
Reserved
Page 49 of 1414
Section 2 CPU