HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1185

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
33.2.12 Branch Destination Register (BRDR)
BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch
destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is
cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by
a power-on reset. Other bits are not initialized by a power-on reset. The eight BRDR registers
have a queue structure and a stored register is shifted at every branch.
33.2.13 Break ASID Register A (BASRA)
BASRA is an 8-bit readable/writable register that specifies ASID which becomes the break
condition for channel A. BASRA is in CCN.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
31
30 to 28 ⎯
27 to 0
Bit
7 to 0
Bit Name
DVF
BDA27 to
BDA0
Bit Name
BASA7 to
BASA0
Initial
Value
0
All 0
⎯
Initial
Value
⎯
R/W
R
R
R
R/W
R/W
Description
BRDR Valid Flag
Indicates whether a branch destination address is
stored. When a branch destination address is fetched,
this flag is set to 1. This flag is cleared to 0 by reading
BRDR.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
These bits are always read as 0. The write value
should always be 0.
Branch Destination Address
Store bits 27 to 0 of the branch destination address.
Description
Store ASID (bits 7 to 0) which is the break condition
for channel A.
Reserved
Break ASID A
Section 33 User Break Controller (UBC)
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