HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1291

SH3-DSP, WITH USB AND LCDC, PB-F

HD6417720BP133BV

Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417720BP133BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
SH7720 Group, SH7721 Group
36.4
36.4.1
Figure 36.2 shows the internal states of the TAP controller. State transitions support the JTAG
standard.
Note: The transition condition is the TMS value at the rising edge of TCK. The TDI value is
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
sampled at the rising edge of TCK; shifting occurs at the falling edge of TCK. For details
on change timing of the TDO value, see section 36.4.3, TDO Output Timing. The TDO is
at high impedance, except with shift-DR and shift-IR states. During the change to TRST =
0, there is a transition to test-logic-reset asynchronously with TCK.
TAP Controller
Operation
1
0
Test -logic-reset
Run-test/idle
0
Figure 36.2 TAP Controller State Transitions
1
1
0
Select-DR-scan
Capture-DR
Update-DR
1
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
0
0
1
0
1
1
0
1
0
0
1
Section 36 User Debugging Interface (H-UDI)
1
0
Select-IR-scan
Capture-IR
1
Update-IR
Pause-IR
Exit1-IR
Exit2-IR
0
0
Shift-IR
1
0
1
1
0
1
0
0
1
Page 1231 of 1414

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