HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 161

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(1)
With double data transfer instructions, X memory and Y memory can be accessed in parallel.
In this case, the specific buses called X bus and Y bus are used to access X memory and Y
memory, respectively. To fetch the CPU instructions, the L bus is used. Accordingly, no conflict
occurs among X, Y, and L buses.
Load instructions for X memory specify the X0 or X1 register as the destination operand. Load
instructions for Y memory specify the Y0 or Y1 register as the destination operand. Store registers
for X or Y memory specify the A0 or A1 register as the source operand. These instructions use
only word data (16 bits). When a word data transfer instruction is executed, the upper word of
register operand is used. To load word data, data is loaded to the upper word of the destination
register and the lower word of the destination register is automatically cleared to 0.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Double data transfer instructions (MOVX.W, MOVY.W)
Legend
XAB
XDB
YAB
YDB
LAB
LDB
CDB
: X bus (address)
: X bus (data)
: Y bus (address)
: Y bus (data)
: L bus (address)
: L bus (data)
: C bus (data)
X memory
Y memory
XAB
[15:0]
Figure 3.4 DSP Registers and Bus Connections
YAB
[15:0]
XDB
[15:0]
YDB
[15:0]
CPU
DSP unit
CDB
[31:0]
DSR
A0
A1
M0
M1
X0
X1
Y0
Y1
A0G
A1G
Section 3 DSP Operating Unit
LAB
[31:0]
LDB
[31:0]
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