HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 245
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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SH7720 Group, SH7721 Group
4.4.4
When a 1- or 4-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number
of virtual addresses are mapped onto a single physical address, the same physical address data will
be recorded in a number of cache entries, and it will not be possible to guarantee data congruity.
The reason that this problem occurs is explained below with reference to figure 4.12.
The relationship between bit n of the virtual address and cache size is shown in the following
table. Note that no synonym problems occur in 4-kbyte page when the cache size is 16 kbytes.
To achieve high-speed operation of this LSI’s cache, an index number is created using virtual
address bits 12 to 4. When a 1-kbyte page is used, virtual address bits 12 to 10 is subject to
address translation and when a 4-kbyte page is used, a virtual address bit 12 is subject to address
translation. Therefore, the physical address bits 12 to 10 may not be the same as the virtual address
bits 12 to 10.
For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following
translation has been performed are recorded in two TLBs:
Virtual address 1 is recorded in cache entry H'000, and virtual address 2 in cache entry H'0C0.
Since two virtual addresses are recorded in different cache entries despite the fact that the physical
addresses are the same, memory inconsistency will occur as soon as a write is performed to either
virtual address.
Consequently, the following restrictions apply to the recording of address translation information
in TLB entries.
1. When address translation information whereby a number of 1-kbyte page TLB entries are
2. When address translation information whereby a number of 4-kbyte page TLB entries are
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Cache Size
16 kbytes
32 kbytes
translated into the same physical address is recorded in the TLB, ensure that the VPN bits 12 is
the same.
translated into the same physical address is recorded in the TLB, ensure that the VPN bit 12 is
the same.
Avoiding Synonym Problems
Virtual address 1 H'0000 0000 → physical address H'0000 0C00
Virtual address 2 H'000 00C00 → physical address H'0000 0C00
Bit n in Virtual Address
11
12
Section 4 Memory Management Unit (MMU)
Page 185 of 1414
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