HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 260
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Section 5 Cache
5.2.1
The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which
invalidates all cache entries), and WT and CB bits (which select either write-through mode or
write-back mode). Programs that change the contents of the CCR1 register should be placed in
address space that is not cached.
Page 200 of 1414
Bit
31 to 4 ⎯
3
2
1
0
Bit Name
CF
CB
WT
CE
Cache Control Register 1 (CCR1)
Initial
Value
All 0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Description
These bits are always read as 0. The write value should
always be 0.
Writing 1 flushes all cache entries (clears the V, U, and
LRU bits of all cache entries to 0). This bit is always
read as 0. Write-back to external memory is not
performed when the cache is flushed.
Write-Back
Indicates the cache’s operating mode for space P1.
0: Write-through mode
1: Write-back mode
Write-Through
Indicates the cache’s operating mode for spaces P0,
U0, and P3.
0: Write-back mode
1: Write-through mode
Indicates whether the cache function is used.
0: The cache function is not used.
1: The cache function is used.
Reserved
Cache Flush
Cache Enable
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
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